Doug Snook

Doug has over forty years of experience in electronics design, the majority as an R&D engineer and project manager at Hewlett Packard and Agilent Technologies, working on various aspects of wireless test instrument development. At Infinetix since 2011, Doug gets great satisfaction working with the Infinetix team to provide creative solutions to our customers’ problems. Doug’s primary engineering focus is in field programmable gate array (FPGA) design, using Verilog, VHDL, and System Verilog code-based methodologies to implement control logic, interface circuitry, and digital signal processing algorithms in application specific and reconfigurable hardware. His FPGA/ASIC background includes extensive usage of Xilinx, Altera, Lattice, and Efinix FPGAs as well as involvement in gate array and standard cell ASIC designs. Doug also has experience in general hardware design (digital, microprocessor, RF, analog), as well as breadth and depth in systems engineering, instrumentation development, and project management. In addition to his responsibilities at Infinetix, Doug has served as an adjunct professor at Gonzaga University, teaching digital logic and FPGA design in the computer engineering department, helping to train the next generation of engineers.

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Infinetix SmartMesh IP™ Services

Infinetix provides a broad range of services associated with the Linear Technology Dust Networks® SmartMesh IP™ technology. Introduction The SmartMesh® technology is a robust wireless sensor network methodology that is especially well suited to commercial and industrial applications in the emerging internet of things (IoT) marketplace. A SmartMesh® network consists of a self-forming, multi-hop mesh of sensor nodes…

SmartMesh IP Cape Device Tree

Infinetix has designed a SmartMesh IP™ Gateway system utilizing a BeagleBone Black (BBB) single board computer and a custom designed add-on board (known as a cape in BeagleBone nomenclature) built around the Linear Technology’s SmartMesh IP™ technology In the BeagleBone Black ecosystem, each cape needs a means to determine pin definition and usage. This is…